Chapter 3 Sections 4 and 5

24-Oct-00

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Chapter 3 Sections 4 and 5

I can always use a review of all the diagrams in this book. They are thrown out there and explained on a bit higher level then I can usually understand

Will the creation of more buses help bus arbitration because different things can be done on different buses or will there still inevitably be problems arising from more than one device wanting to use a bus. For example, with Figure 3-50 on page 185, if there were fewer separate buses or more, would there be a significant difference in access time and bus arbitration?

Better explanation of the programming assignment; in particular, what Tanenbaum means by a wiring list.

I was just wondering since their is so much information in this chapter, i just wanted to know which information is more important to know. I realize that what you go over in class are the more important key points, but if their are other things i should be looking for in the reading i would like to know.

A lot of the diagrams were hard to follow in this section.

Is there a processor that is considered the best in all fields?

I need explaining on Address Decoding and memory-mapped I/O.

I need clarifying on how synchronous buses use the clock to work and in general how asynchronous buses work.

Author: Lillian N. Cassel

Email: cassel@acm.org

Home Page: http://lcassel.csc.villanova.edu

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