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Main.ComputerHardwareOrganization
r1.8 - 27 Sep 2007 - 23:32 - Main.nova
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Computer Hardware Organization
Digital logic
Logic expressions
Transformation
minimization
normal forms
Digital systems
Electronic circuits
logic gates
Combinational Circuits
Multiplexers
Decoders
Encoders
PLA
switching
Feedback Circuits
counters
adders
flip-flops
registers
Design Considerations
layout
placement
routing
VLSI
concurrency
constraints
delay
race conditions
fanout
heat
speed
Integrated circuits
Hardware Language
Register transfer notation
functional considerations
Hardware description languages (e.g. VHDL)
Logic Design
General
Design Styles
Cellular arrays and automata
Combinational logic
Logic arrays
Memory control and access
Memory used as logic
Parallel circuits
Sequential circuits
Reliability, Testing and Fault-Tolerance
Built-in tests
Error-checking
Redundant design
Test generation
Testability
Design Aids
Automatic synthesis
Hardware description languages
Optimization
Simulation
Switching theory
Verification
Miscellaneous
Integrated Circuits
General
Types and Desgin Styles
Advanced technologies
Algoritms implemented in hardware
Gate arrays
Input/output circuits
Memory technologies
Microprocessors and microcomputers
Standard cells
VLSI
Design Aids
Graphics
Layout
Placement and routing
Simulation
Verification
Reliability and Testing
Built-in tests
Error-checking
Redundant design
Test generation
Testability
Miscellaneous
Performance and Reliability
General
Reliability, Testing and Fault-Tolerance
Performance Analysis and Design
Miscellaneous
Machine level representation of data
Storage units
Bits
Bytes
Words
Information Representation
Size
Range
Precision
Accuracy
Binary data
Encrypted
Compressed
Compiled code
Numeric
Integer
Twos complement
Sign magnitude
Ones complement
Non Integer
Fixed point
Floating point * IEEE standard
Character
standards
ASCII
UNICODE
EBCDIC
formats
font
color
size
style
Graphical
vector
raster
pixels
Multimedia
sound
video
image
standards
jpg
tiff
gif
Complex data
Record (struc)
String
Array
Multiple precision
Pointer (aka address)
Programs
Instruction
Format
Addressing modes
Instruction types
data manipulation
control
sequential
loop
decision (if)
subroutine call
parallel
interrupt
input/output
Encoding standards
Compression
Integrity
Error correcting/dectecting codes
parity
Hamming code
Fault handling
Machine Organization
Design Structure
vonNeumann
Processor Count
Single Processor
Multi Processor
Multi Core Processsor
Embedded system
Special Purpose processors
Graphics processor
Games processor
Other special purpose processors
Register-Transfer-Level Implementation
General
Design
Arithmetic and logic units
Control design
Data-path design
Memory Design
Styles (e.g. parallel, pipeline, special-purpose)
Design Aids
Automatic synthesis
Hardware design languages
Optimization
Simulation
Verification
Reliability, Testing and Fault-Tolerance
Built-in tests
Error-checking
Redundant design
Test generation
Testability
Miscellaneous
Central Processing Unit
Processor system design
clock
control
data bus
address bus
Address decoding
Memory interfacing
Interfaces
parallel
serial
Timers
System firmware
Instruction Set Architecture
Complex Instruction Set Computer (CISC)
Reduced Instrucion Set Computer (RISC)
Very Large Instruction Word (VLIW)
Short vector instruction sets
Compiler requirements
Multimedia application connections
Streaming extensions
Security requirements
Performance
Pipeline
Hazards * Structural * Data * Data Control
Superscalar architecture
Multithreading
Scalability
Metrics
clock rate
MIPS
Cycles per instruction
benchmarks
strengths & weaknesses
averaging
arithmetic
geometric
harmonic
Amdahl's law
Moore's law
Control Unit
Design Considerations
Microprogramming
Hard wiring
Operation
Machine Cycle
Fetch Instruction
Decode
Fetch operands
Execute
Write result
Arithmetic - Logic Unit
Design Considerations
Performance
Functional Units
Adders
Half Adders
Full Adders
Fast Adders
Multipliers
Logic Unit (aka Boolean Unit)
Floating Point Unit
Algorithms
Implemenation
Standards
Data path
Bus
Single
Multiple
Protocols * Arbitration
Storage
Latency
Bandwidth
Cycle time
Organization
Interleaving
Registers
Accumulator
Program Counter
Instruction Register
Stack Pointer
Memory Buffer Register
Memory Address Register
Interrupt bits (register)
Processor Status Word
General Purpose Registers
Cache
Characteristics
Address mapping
Block size / line size
Replacement policy
Store policy
write-back policies
write through policies
Performance
Branch prediction
Prefetching
Speculative execution
Levels
L0
L1
L2
RAM
DIMM
DRAM
SDRAM
ROM
EPROM
EEPROM
External Storage
Connection
Directly connected
Off line
Networked
RAID architectures
Magnetic
Tape
Disk
RAID
SMART Technology
Optical
CD-ROM
DVD
Flash drive
Electronic
Smart cards
Mobile phones
MP3 players
Network Storage
Other External Storage
Input - Output and Data Communications
Performance
fault detection
Interface / Communication
Handshaking
Buffering
Double buffering
Programmed
Interrupt driven
Interrupt structures
Interrupt controlers
vectored interrupt structures
prioritized interrupts
overhead
reentrant code
Direct Memory Access
Device Drivers
Analog to Digital Converters
Digital to Analog Converters
Secondary Storage
Input Devices
Keyboard
Mouse
Voice Input device
Data gathering devices
Temperature Probe
Geographical Positioning System
Biometric
Other sensors
SMART card reader
Graphic tablet
Camera
Output Devices
Printer
Monitor/Display
Speaker
Alarm
Control devices
Other output devices
Data communications
Interconnections (Subsystems)
Asynchronous/synchronous operation
Fiber optics
Interfaces
Parallel I/O
Topology (e.g. bus, point-to-point)
Radio
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